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Integrated Circuit Systems, Inc.
ICS9148-47
Pentium/ProTM System Clock Chip
General Description
The ICS9148-47 is part of a reduced pin count two-chip clock solution for designs using an Intel BX style chipset. Companion SDRAM buffers are ICS9179-11 and 12. There are two PLLs, with the first PLL capable of spread spectrum operation. Spread spectrum typically reduces system EMI by 8-10dB. The second PLL provides support for USB (48MHz) and 24MHz requirements. CPU frequencies up to 100MHz are supported. The I2C interface allows stop clock programming, frequency selection, and spread spectrum operation to be programmed. Clock outputs include two CPU (2.5V or 3.3V), seven PCI (3.3V), one REF (3.3V), one IOAPIC (2.5V or 3.3V), one 48MHz, and one selectable 48/24MHz.
Features
Generates system clocks for CPU, PCI, IOAPIC , 14.314 MHz, 48 and 24MHz. Supports single or dual processor systems Skew from CPU (earlier) to PCI clock 1 to 4ns Separate 2.5V and 3.3V supply pins 2.5V outputs: CPU, IOAPIC 3.3V outputs: PCI, REF No power supply sequence requirements 28 pin SOIC Spread Sectrum operation optional for PLL1 CPU frequencies to 100MHz are supported.
Pin Configuration Block Diagram
28 pin SOIC
Power Groups
VDD = Supply for PLL core VDD1 = REF0, X1, X2 VDD2 = PCICLK_F, PCICLK (0:5) VDD3 = 48MHz VDDL = CPUCLK (0:1) VDDL1=IOAPIC
Ground Groups
GND = Ground Source Core GND1 = REF0, X1, X2 GND2 = PCICLK_F, PCICLK (0:5) GND3=48MHz GNDL = CPUCLK (0:1)
Pentium is a trademark on Intel Corporation. 9148-47 Rev D 08/04/98
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9148-47
Pin Descriptions
PIN NUMBER 1 2 3 4 5, 6, 7, 8, 10, 11 6, 9 12 13 14 15 16 17 18 19 20 21, 22 23 24 25 26 27 28 PIN NAME X1 X2 GND2 PCICLK_F PCICLK (0:5) VDD2 VDD3 48MHz 24/48MHz GND3 SEL100/66.6# SCLK SDATA GND VDD CPUCLK (1:0) VDDL IOAPIC VDDL VDD1 REF0/SEL 48# GND1 TYPE IN OUT PWR OUT OUT PWR PWR OUT OUT PWR IN IN IN PWR PWR OUT PWR OUT PWR PWR OUT/IN PWR DESCRIPTION XTAL_IN 14.318MHz Crystal input, has internal 33pF load cap and feed back resistor from X2 XTAL_OUT Crystal output, has internal load cap 33pF Ground for PCI outputs Free Running PCI output PCI clock outputs. TTL compatible 3.3V Power for PCICLK outputs, nominally 3.3V Poer for 48MHz Fixed CLK output @ 48MHz Fixed CLK output; 24MHz if pin 27 =1 at power up, 48MHz if pin 27=0 at power up. Ground for 48MHz Select pin for enabling 100MHz or 66.6MHz H=100MHz, L=66.6MHz (PCI always synchronous 33.3MHz) Clock input for I2C input Data input for I2C input Ground for CPUCLK (0:1) Power for PLL core CPU and Host clock outputs nominally 2.5V Power for CPU outputs, nominally 2.5V IOAPIC clock output 14.318MHz. Power for IOAPIC Power for REF outputs. 14.318MHz clock output/Latched input at power up. When low, pin 14 is 48MHz. Ground for REF outputs, X1, X2.
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ICS9148-47
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:

Send the address D2(H) . Send two additional dummy bytes, a command code and byte count. Send the desired number of data bytes.
See the diagram below:
Clock Generator Address (7 bits) + 8 bits dummy command code + 8 bits dummy Byte count Data Byte 1 Data Byte N
A(6:0) & R/W# D2(H)
ACK
ACK
ACK
ACK
ACK
Note that the acknowledge bit is sent by the clock chip, and pulls the data line low. There is no minimum of data bytes that must be sent.
How to Read:

Send the address D3(H). Send the byte count in binary coded decimal Read back the desired number of data bytes
See the diagram below:
Clock Generator Address (7 bits) A(6:0) & R/W# D3(H) ACK
Byte Count
ACK
Data Byte 1
ACK
Data Byte N
The following specifications should be observed: 1. Operating voltage for I2C pins is 3.3V 2. Maximum data transfer rate (SCLK) is 100K bits/sec.
3
ICS9148-47
Serial Bitmap
Byte 3: Functionality & Frequency Select & Spread Slect Register
Bit 7 Bit 654 000 001 010 011 100 101 110 111 CPU 68.5 75.0 83.3 66.6 103 112 133.3 100 Description (Reserved) PCI 34.25 37.5 41.6 33.3 34.3 37.3 44.43 33.33 Spread Percentage 0.5% Center 0.5% Center 0.5% Center 0.5% Center 0.5% Center 0.5% Center 0.5% Center 0.5% Center PWD 0
Byte 5:
Bit 7 6 5
0
Pin# 4 11 10 8 7 6 5
Pin Name PCICLK_F PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
PWD 1 1 1 0 1 1 1 1
6:4
4 3 2
3 2 10
0 - Frequency is selected by hardware select SEL100/66.6# 1 - Frequency is selected by 6:4 above (Reserved) 00 - Normal operation 01 - Test mode 10 - Spread sprectrum ON 11 - Tristate all outputs
0
1 0
Description Bit Value = 0 Bit Value = 1 Disabled Enabled (low) Disabled Enabled (low) Disabled Enabled (low) (Reserved) (Reserved) Disabled Enabled (low) Disabled Enabled (low) Disabled Enabled (low) Disabled Enabled (low)
00
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Byte 4:
Bit 7 6 5 4 3 2 1 0 Pin# 21 22 Pin Name CPUCLK1 CPUCLK0 PWD 1 0 1 Description Bit Value = 0 Bit Value = 1 (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Disabled Enabled (low) (Reserved) (Reserved) (Disabled) Enabled (low)
Byte 6:
Bit 7 6 5 4 3 2 1 0 Pin# 24 27 27 Pin Name IOAPIC REF0 REF0 PWD 0 0 1 0 0 0 1 1 Description Bit Value = 0 Bit Value = 1 (Reserved) (Reserved) (Reserved) (Reserved) Disabled Enabled (low) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Disabled) Enabled (low) (Disabled) Enabled (low)
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default
Notes: 1 = Enabled; 0 = Disabled, outputs held low For pin 27, there are 2 output stages together for 1 pin. These 2 latches must be both 0 or 1 simultaneously or there will be a short to ground if one is disabled and the other is running.
4
ICS9148-47
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Input Capacitance1 Transition Time1 Settling Time1 Clk Stabilization 1 Skew1
1
SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP66 IDD3.3OP100 IDD3.3PD Fi CIN CINX Ttrans Ts TSTAB TAGP-PCI1
CONDITIONS
MIN 2 VSS-0.3
TYP
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors -5 VIN = 0 V; Inputs with pull-up resistors -200 CL = 0 pF; Select @ 66MHz CL = 0 pF; Select @ 100MHz CL = 0 pF; With input address to Vdd or GND VDD = 3.3 V; Logic Inputs X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq. VT = 1.5 V; 1 27
0.1 2.0 -100 60 66 3 14.318 36 5
MAX UNITS VDD+0.3 V 0.8 V A 5 A A 170 170 650 mA A MHz 5 45 3 3 pF pF ms ms ms ns 4
3.5
Guaranteed by design, not 100% tested in production.
5
ICS9148-47
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Operating Supply Current Power Down Supply Current Skew
1 1
SYMBOL IDD2.5OP66 IDD2.5OP100 IDD2.5PD tCPU-AGP tCPU-PCI2
CONDITIONS CL = 0 pF; Select @ 66.8 MHz CL = 0 pF; Select @ 100 MHz CL = 0 pF; With input address to Vdd or GND VT = 1.5 V; VTL = 1.25 V
MIN
TYP 16 23 10
MAX 72 100 100 1 4
UNITS mA mA A ns ns
0 1
0.5 2.6
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLK
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; C L = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, Cycle-to-cycle Jitter, One Sigma Jitter, Absolute
1
SYMBOL VOH2B VOL2B IOH2B IOL2B tr2B t f2B
1 1
CONDITIONS IOH = -12.0 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
MIN 2
19
TYP 2.3 0.2 -41 37 1.25 1
MAX UNITS V 0.4 V -19 mA mA 1.6 1.6 55 175 250 150 +250 ns ns % ps ps ps ps
d t2B1 tsk2B
1
45
48 30 150 40
tjcyc-cyc2B1 tj1s2B1 tjabs2B1
-250
140
Guaranteed by design, not 100% tested in production.
6
ICS9148-47
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Skew
1 1 1 1 1
SYMBOL VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 tsk1 tj1s1 tjabs1
CONDITIONS IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.4
16
TYP 3.1 0.1 -62 57 1.5 1.1
MAX UNITS V 0.4 V -22 mA mA 2 2 55 500 150 500 ns ns % ps ps ps
Duty Cycle
45
50 140 17
Jitter, One Sigma Jitter, Absolute
1
1
-500
70
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Skew1 Jitter, One Sigma Jitter, Absolute
1 1 1 1 1 1
SYMBOL VOH4B VOL4B IOH4B IOL4B Tr4B Tf4B Dt4B tsk4B
1
CONDITIONS IOH = -18 mA IOL = 18 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
MIN 2
29
TYP 2.2 0.33 -41 37 1.3 1.1
MAX UNITS V 0.4 V -28 mA mA 1.6 1.6 55 250 3 5 ns ns % ps % %
Duty Cycle
45
54 60 1
Tj1s4B Tjabs4B
-5
Guaranteed by design, not 100% tested in production.
7
ICS9148-47
Electrical Characteristics - 48, 24 MHz
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1 1
SYMBOL VOH5 VOL5 IOH5 IOL5 tr5 tf5 dt5 tj1s5 tjabs5
CONDITIONS IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.6
16
TYP 3 0.14 -44 42 1.2 1.2
MAX UNITS V 0.4 V -22 mA mA 4 4 55 3 5 ns ns % % %
Duty Cycle
45
52 1 3
Jitter, One Sigma Jitter, Absolute
1
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1 1
SYMBOL VOH5 VOL5 IOH5 IOL5 tr5 tf5 dt5 tj1s5 tjabs5
CONDITIONS IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.6
29
TYP 3.1 0.17 -44 42 1.4 1.1
MAX UNITS V 0.4 V -22 mA mA 2 2 57 3 5 ns ns % % %
Duty Cycle
47
54 1 3
Jitter, One Sigma Jitter, Absolute
1
1
Guaranteed by design, not 100% tested in production.
8
ICS9148-47
LEAD COUNT
28L 0.704
SOIC Package
DIMENSION L
Ordering Information
ICS9148M-47
Example:
ICS XXXX M - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type M=SOIC Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
9

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